NVIDIA has announced NVHBM, a custom high-bandwidth memory technology built into the HBM base die rather than on the compute die itself. This approach, which NVIDIA plans to use in its future GPUs, is now extended to third-party XPU customers through NVLink Fusion.
The main idea behind it is rather simple, since standard HBM puts the memory controller on the compute die, that is consuming silicon that could otherwise be used for compute. NVHBM moves that controller into the 3D HBM stack, which has a notable effect on performance and efficiency.
Compared to standard HBM4E, NVIDIA claims up to 30% more memory bandwidth, 15% lower HBM power consumption, and up to 25% more usable compute die area on the processing unit. The area savings come primarily from a redesigned physical memory interface. Standard HBM uses wider interface connections that increase package footprint, on the other hand, the NVHBM custom PHY reduces that I/O area by up to 67% compared to JEDEC HBM4E.
Also, the narrower interface simplifies interposer routing, freeing up to 80% more usable silicon across the layout. The reduced PHY footprint also means fewer routing constraints on the interposer, which matters when you're trying to pack multiple HBM stacks alongside a large compute die, explains NVIDIA in a dedicated blog post.
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